腾讯网

谈谈Verilog和SystemVerilog简史，FPGA设计是否需要学习SystemVerilog

SystemVerilog标准（SV-2009）发布距今已近十余年，在验证领域已经大放异彩，但是在设计领域（尤其FPGA领域）使用的还是比较少，虽然市场上已经发布了几本相关书籍，但是在使用上或者学习上还是有点缺陷的，这篇文章是SystemVerilog建模及仿真系列教程的第一篇 ...
电子工程专辑

新书上架！芯片设计入门必看：SystemVerilog “零基础通关手册” 来了！

想入门数字IC设计与验证？想搞懂SystemVerilog这门核心语言？ 这本由日本资深架构设计师篠塚一也撰写的《SystemVerilog入门指南》，直接帮你打通从理论到实操的任督二脉！ 作为IEEE1800-2017标准的权威解读，它不仅兼容Verilog，更融合硬件描述与验证功能，414页内容 ...
电子工程专辑

【文档必备】Verilog、SystemVerilogIEEE标准规范

作为逻辑工程师，在FPGA和数字IC开发和设计中，一般采用verilog，VHDL或SystemVerilog等作为硬件描述语言进行工程设计，将一张白板描绘出万里江山图景。 工程师在利用硬件描述语言进行数字电路设计时，需要遵守编译器支持的Verilog,VHDL或systemverilog标准规范，并 ...
Design-Reuse

AMIQ EDA Introduces Duplicate Code Detection in Its Verissimo SystemVerilog Testbench Linter

AMIQ EDA, a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis ...
EDN

Novas linter finds SystemVerilog errors

San Jose, Calif. — Novas Software Inc.'s nLint IC coding-error-detection product now supports SystemVerilog. The tool previously supported Verilog and VHDL. “NLint analyzes code and gives pointers for ...
Design-Reuse

Synopsys Announces Source-Code License for SystemVerilog Verification Library

VMM Standard Library Enables Adoption of Techniques in the ARM-Synopsys Verification Methodology Manual (VMM) for SystemVerilog MOUNTAIN VIEW, Calif. -- Sept. 21, 2005-- Synopsys, Inc., a world leader ...
EDN

Translator bridges Vera code to SystemVerilog 3.1

Santa Cruz, Calif. – Startup VeriEZ Solutions Inc. has announced fourth-quarter availability of EZTranslate, which will serve as a bridge between Synopsys Inc.'s Vera-based verification environments ...
Electronic Design

Find the Fastest Route to Portable Stimulus Tests with SystemVerilog

Download this article in PDF format. The Portable Stimulus Specification (PSS) is all about reusing commonly used test atoms to create new scenarios more quickly. It saves us from wasting precious ...
Hackaday

Visualizing Verilog Simulation

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some ...